From xen-devel-bounces@lists.xen.org Fri Mar 27 16:37:46 2015 Received: (at maildrop) by bugs.xenproject.org; 27 Mar 2015 16:37:46 +0000 Received: from lists.xen.org ([50.57.142.19]) by bugs.xenproject.org with esmtp (Exim 4.80) (envelope-from ) id 1YbXGU-00089W-0X for xen-devel-maildrop-Eithu9ie@bugs.xenproject.org; Fri, 27 Mar 2015 16:37:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YbXFh-00085e-Fv; Fri, 27 Mar 2015 16:36:57 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YbXFg-00085Z-On for xen-devel@lists.xen.org; Fri, 27 Mar 2015 16:36:56 +0000 Received: from [85.158.137.68] by server-10.bemta-3.messagelabs.com id B7/A0-14673-72785155; Fri, 27 Mar 2015 16:36:55 +0000 X-Env-Sender: julien.grall@linaro.org X-Msg-Ref: server-14.tower-31.messagelabs.com!1427474215!9308678!1 X-Originating-IP: [209.85.212.171] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 6.13.6; banners=-,-,- X-VirusChecked: Checked Received: (qmail 10314 invoked from network); 27 Mar 2015 16:36:55 -0000 Received: from mail-wi0-f171.google.com (HELO mail-wi0-f171.google.com) (209.85.212.171) by server-14.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 27 Mar 2015 16:36:55 -0000 Received: by wibbg6 with SMTP id bg6so33160113wib.0 for ; Fri, 27 Mar 2015 09:36:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:message-id:date:from:user-agent:mime-version:to :cc:subject:references:in-reply-to:content-type :content-transfer-encoding; bh=3X9kWZ20/H/Y5QRNC1UP7oz5cXgHYB4WUBMweCCE2C0=; b=ZT4JmLh7t04a9l8q7T+xft8PAn+Kv/Xg39flD0D5CW9WJ6m/dHPzt7dNXrvCAbZD5R 2B1/UgYJRFWZsMa44XVnJnrH6UjNsHewJodavfUbFtXyDsmUGCtOPWITVQniX6tpfHlb HMgzOFIjx1G+U2o/+qW5/4lEjiQDSNyNNFwPKQpfkZda+buQiC6Eu9sCB5GMtn2XJeuu DDSaMzCN5h/8Sl1fSgGMDyJeKlvPo7Ktuhf/JIHi5/vydsUWaxzM32GyzEPo+JUWQoMk 6O+Q1BFfcco/D2jD6c/hGlSoZTQH6E6otRaeDHln6rMrxdPEsDPX3o94i2q09qWLs1G/ K73Q== X-Gm-Message-State: ALoCoQnUovuXrnmj6kjGpo2VkFoXTTiFZzUVqSIqcH96Ut3TjknjnZPVN96PkjrGk07Vqzmf30i0 X-Received: by 10.180.126.37 with SMTP id mv5mr34836962wib.16.1427474215014; Fri, 27 Mar 2015 09:36:55 -0700 (PDT) Received: from [10.80.2.139] ([185.25.64.249]) by mx.google.com with ESMTPSA id jt8sm4167034wid.4.2015.03.27.09.36.53 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Mar 2015 09:36:54 -0700 (PDT) Message-ID: <5515870C.1080702@linaro.org> Date: Fri, 27 Mar 2015 16:36:28 +0000 From: Julien Grall User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Icedove/31.3.0 MIME-Version: 1.0 To: Ian Campbell , xen-devel@lists.xen.org References: <1427466798.13935.158.camel@citrix.com> <1427466824-31967-8-git-send-email-ian.campbell@citrix.com> In-Reply-To: <1427466824-31967-8-git-send-email-ian.campbell@citrix.com> Cc: tim@xen.org, stefano.stabellini@eu.citrix.com Subject: Re: [Xen-devel] [PATCH v4 08/15] xen: arm: don't pretend to handle cache maintenance by set/way X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org Hi Ian, On 27/03/15 14:33, Ian Campbell wrote: > We set HCR_EL2.TSW but only (sort of) handle 32-bit access to DCCISW > but not the other two registers, nor any 64-bit access. Add handlers > for all of these. We don't set HCR_EL2.TSW so DCCISW is not trapped. > diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h > index c2dcb66..cf3d6cc 100644 > --- a/xen/include/public/arch-arm.h > +++ b/xen/include/public/arch-arm.h > @@ -161,6 +161,11 @@ > * > * - The device tree Xen compatible node is fully described under Linux > * at Documentation/devicetree/bindings/arm/xen.txt. > + * > + * - Cache maintenaince operations by set/way ("dc isw|cisw|csw" and > + * the equivalent cp15 registers) are not available when running > + * under Xen and will result in an undefined instruction exception > + * delivered to the guest. > */ set/way operations is used by Linux ARM32 in order to flush all the cache. Injecting an undefined instruction would make guest unusable. Regards, -- Julien Grall _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel